With the rapid development of semiconductor manufacturing technology, more semiconductor devices need to be integrated in one chip in order to obtain a faster operating speed, a larger memory space and more functions. With the increasing integration of devices in semiconductor chips, the critical dimensions of the devices are getting smaller.
The conventional integrated circuit (IC) packaging technique applies bonding wires and bonding pads to obtain electrical interconnection of the chips, which may enlarge the sizes of packages. Therefore, the through silicon via (TSV) technique, which is a new 3D packaging technology, is developed to obtain a 3D chip stacking structure that provides higher packaging density to reduce the packaging sizes. The TSV technique can also increase the operating speed of the chips and reduce the power consumption thereof.
By applying the TSV technique, a TSV structure is formed to vertically interconnect the chips or wafers. FIGS. 1 through 4 are schematic cross-sectional views of intermediate structures of a TSV structure formed by a conventional TSV technique. Referring to FIG. 1, a plurality of MOS transistors 12 are formed on a surface of a silicon substrate 10, an interlayer dielectric layer 11 is formed on the MOS transistors, and an opening 13 is formed through the interlayer dielectric layer 11 and in the substrate 10. The opening 13 has a bottom and sidewalls in the silicon substrate 10.
Thereafter, a silicon oxide layer 15 is formed by depositing silicon oxide material on the bottom and the sidewalls of the opening 13, and on the interlayer dielectric layer 11, as shown in FIG. 2. Thereafter, referring to FIG. 3, a copper layer 16 is formed by depositing a copper material until the copper completely fills the opening 13 and covers the silicon oxide layer 15. Thereafter, referring to FIG. 4, a portion of the silicon oxide layer 15 and a portion of the copper layer 16 are removed by a chemical mechanical polishing (CMP) process until the interlayer dielectric layer 11 is exposed.
Specifically, the CMP process includes removing the copper layer 16 on the silicon oxide layer 15 until the silicon oxide layer 15 is exposed, and removing the silicon oxide layer 15 and the copper layer 16 by using the interlayer dielectric layer 11 as a stop layer. In the conventional TSV technique, the silicon oxide layer 15 is used to insulate the silicon substrate 10 from the copper layer 16. The silicon oxide layer 15 has generally a relatively large thickness ranging from about 1000 Å to about 2000 Å. As a result, the removal of the silicon oxide layer may takes a long period of time. However, in the CMP process, a removal rate of the silicon oxide layer 15 is larger than a removal rate of the copper layer 16. Therefore, when the CMP process is completed, the silicon oxide layer 15 on the interlayer dielectric layer 11 is completely removed, but the copper layer 16 may have an elevated surface that is protruded over the surface of the interlayer dielectric layer 11, so that a protruding portion is formed. The protruding portion may affect the performance of the TSV structure.
Therefore, there is a need to provide a method for forming a TSV structure that is capable of improving the performance of the TSV structure.